PLDs are a well-known type of integrated circuit (IC) that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Some PLDs, such as the Xilinx Virtex® FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration data bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Unlike custom ICs, an FPGA includes a clock signal network that is pre-fabricated and programmable. As such, the programmability of the FPGA clock signal network must be flexible enough to meet the various connectivity, skew, and latency objectives for a variety of clock signal fanout and load placement topologies. Modern FPGAs, therefore, constrain logic resources to specific regions within the FPGA, i.e., clock regions. Each clock region may then be programmably allocated a fixed number of clock signals, where the fixed number of clock signals is programmably selected from a larger number of clock signals that are available on the FPGA.
Accordingly, a large number of clock signals may exist on the FPGA to provide flexibility to each clock region, while at the same time mitigating the costs associated with constructing large numbers of clock networks throughout the FPGA. Such flexibility, however, yields a propensity for inefficient clock signal provisioning within each clock region because the capacitive loading within each clock region is not optimized. As such, excessive leakage and dynamic power may be consumed within each clock region as a consequence of charging and discharging the capacitive loads within each clock region.
Efforts continue, therefore, to reduce leakage and dynamic power consumption within an IC, such as an FPGA, by recognizing the structure and programmability of the clock network architecture within the FPGA. Using architectural knowledge of the FPGA, efficient usage of the pre-fabricated clock network may be realized to reduce the capacitive load within each clock region, thereby reducing the leakage and dynamic power consumed within each clock region of the FPGA.